Low-k interlevel dielectrics technology

Semiconductor manufacturers have been shrinking transistor size in integrated circuits (IC) to improve chip performance. This has resulted in increased speed and device density, both of which were described well by what is known as Moore’s Law – chip performance will double every ~18 months. The speed of an electrical signal in an IC is governed by two components – the switching time of an individual transistor, known as transistor gate delay, and the signal propagation time between transistors, known as RC delay (R is metal wire resistance, C is interlevel dielectric capacitance): ( ) , 4 2 2 2 2 2 T L P L delay RC + = ρε where: ρ is metal resistivity, ε – permittivity of the interlevel dielectric (ILD) (ε is ch, T – metal thickness.